1. Field of the Invention
The present invention relates to a semiconductor integrated circuit and a method of testing the same and, more particularly, to technology providing a mechanism for obtaining a grasp of a delay characteristic inside a semiconductor integrated circuit and adaptively controlling a voltage of supplied power to achieve a reduction of power consumption.
2. Description of the Related Art
In the process of producing semiconductor integrated circuits, variations arise in the characteristics of the principal components of the semiconductor integrated circuits, such as the transistors, the logical gates configured by combinations of the same, and other circuit elements, due to fluctuations in the process conditions.
For example, when considering the case where the threshold voltage of a transistor varies due to such fluctuations in production, the influence thereof appears in the power supply voltage supplied to the produced semiconductor integrated circuit and its operation speed. If produced so that the threshold voltage becomes a value slightly lower than the design value, the operation speed becomes faster. On the other hand, if produced so that the threshold voltage becomes a value slightly higher than the design value, the operation speed becomes slower.
In the shipment tests of produced semiconductor integrated circuits, it is necessary to guarantee their operations and to check the operation at the power supply voltage and the operation frequency in the set product in which the semiconductor integrated circuit is finally mounted. Namely, the shipment test is carried out by the shipment specifications of the power supply voltage and the operation frequency further considering an extra margin in usage. In general, a semiconductor integrated circuit is designed so as to pass this shipment test even if its operation speed becomes slower due to fluctuations in production. For this reason, when the operation speed becomes faster, the semiconductor integrated circuit may often operate at an even faster operation frequency or at an even lower power supply voltage than the shipment specification.
From such a viewpoint, in recent years, a method of adaptively controlling the operation frequency of a semiconductor integrated circuit or the power supply voltage to be supplied in accordance with fluctuations in production has been reported (see Japanese Unexamined Patent Publication (Kokai) No. 2002-505497).
In the technology described in Japanese Unexamined Patent Publication (Kokai) No. 2002-505497, integrated circuits are divided into groups according to their performance at the time of the test. The integrated circuits that are found to operate at faster speeds are designated by the parameter of a faster clock frequency, while the integrated circuits which only operate at slower speeds are designated by the parameter of a slower clock frequency. Integrated circuits produced in the same way, therefore, are given different performance specifications.
In semiconductor integrated circuits such as microprocessors and general purpose memories, products having the same functions but different operation frequencies are therefore sold. Semiconductor integrated circuits having performance specifications matching individual applications of the set products are accordingly selectively mounted. As a result, this grouping according to the clock frequency can be said to be an effective approach.
Japanese Unexamined Patent Publication (Kokai) No. 2001-36008 discloses measuring the delay time of a critical path in a semiconductor integrated circuit, comparing this delay time with a predetermined time, and controlling the power supply voltage so that the delay time becomes faster than the predetermined time.